Department of Computer Science, The University of York

Dr Leandro Soares Indrusiak  
Reader in Real-Time Systems  

Open Projects 2021

BEng and MEng projects for the academic year 2021/2022

Leandro Soares Indrusiak

 

lsi500.001 - Genetic Algorithms for Real-Time Network-on-Chip Optimisation: reducing downstream indirect interference

This project will involve the design and fine-tuning of a genetic algorithm (GA) pipeline to optimise allocation of tasks to processing cores interconnected using a Network-on-Chip (NoC). The optimisation objective is to to satisfy end-to-end hard real-time guarantees including computation latency over the cores and communication latency over the NoC. Existing work on static mapping of hard real-time tasks over homogeneous NoCs, linked below, should be used as basis for this project. Specifically, the project should use the latest schedulability test that considers downstream indirect interference to guide the evolutionary process towards fully schedulable allocations. The main goal of the project is to investigate the impact of downstream indirect interference on the end-to-end schedulability of applications running over NoCs, and the effectiveness of GAs on reducing that impact.

A successful project will extend and experiment with a GA suite (e.g. NSGA-II, Watchmaker Framework), and a fitness function based on end-to-end schedulability analysis of priority-preemptive Networks-on-Chip (a Java implementation will be provided by the supervisor). Extensive experimental work will analyse different configurations of the GA and their impact on the convergence towards full schedulability in different NoC platforms (e.g different topologies, different application profiles). At Master level, optimisation of the performance of the fitness function should be considered (i.e. start the search using a lightweight schedulability test and then use more sophisticated tests as the search converges towards full schedulability).

Requirements: good programming skills in Java

Desired: EMBS module, basics of Networks-on-Chip, real time systems

Suitable for: BEng CS, BEng CSEmb, MEng CS, MEng CSEmb, BEng CSAI, MEng CSAI, MSc ACS

Related work:
  • L.S. Indrusiak, A. Burns, B. Nikolic, Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs. In: Proc. IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018. p. 219-224.
  • L.S. Indrusiak, End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration. Journal of Systems Architecture, vol. 60, no. 7, 2014. p. 553-561.
  • M. Norazizi Sham Mohd Sayuti, Leandro Soares Indrusiak, Real-time low-power task mapping in Networks-on-Chip. In: Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013. p. 14-19.
     

    lsi500.002 - Genetic Algorithms for Task Mapping over Real-Time Networks-on-Chip: reducing vulnerability against timing attacks

    This project will involve the configuration of a genetic algorithm (GA) pipeline to evolve task mappings that are able to satisfy hard real-time guarantees over Networks-on-Chip (NoCs) while reducing vulnerability against timing attacks on communication packets. Existing work on static mapping of hard real-time tasks over NoCs, linked below, has exploited packet route randomisation, and should be used as basis for this project. The main goal of the project is to review different timing attacks, understand which features of the NoC platform provide side-channels for those attacks, and try to reduce the information available through such side channels while at the same time guaranteeing full schedulability of the application.

    A successful project will extend and experiment with a GA suite (e.g. NSGA-II), and a fitness function based on end-to-end schedulability analysis of priority-preemptive Networks-on-Chip. Extensive experimental work will analyse different configurations of the GA and their impact on the convergence towards reduced vulnerability to attacks and full schedulability in different NoC platforms (e.g different topologies, different communication patterns). At Master level, an additional comparison with a constructive mapping heuristic should also be performed.

    Requirements:

    Desired: good programming skills in Java, basics of Networks-on-Chip, basics of response time analysis for priority-preemptive real time systems

    Suitable for: BEng CS, BEng CSEmb, MEng CS, MEng CSEmb, MSc Cyber

    Related work:
  • L. S. Indrusiak, J. Harbin, C. Reinbrecht, M. J. Sepulveda, Side-channel protected MPSoC through secure real-time networks-on-chip. Microprocessors and Microsystems, vol. 68, 2019, p. 34-46.
  • L.S. Indrusiak, End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration. Journal of Systems Architecture, vol. 60, no. 7, 2014. p. 553-561.
  • M. Norazizi Sham Mohd Sayuti, Leandro Soares Indrusiak, Real-time low-power task mapping in Networks-on-Chip. In: Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013. p. 14-19.

    lsi500.014 - Discrete-event simulation of wormhole networks

    Wormhole networks are widely used in domains where buffering overheads should be avoided, such as in supercomputer interconnects and on-chip networks. This project will involve the design and implementation of a fast and accurate simulator for wormhole networks. While several simulators can be customised to simulate such networks, a simple and dedicated simulator for this particular switching mechanism can provide high performance and low memory footprint, which can be useful for the massively-parallel execution of simulations that are needed in optimisation processes.

    A successful project will produce a simulation environment that allows the instantiation of wormhole network routers following any arbitrary topology, as well as packet producers and consumers. Different choices of routing and arbitration mechanisms should be supported, and future extensibility should a desirable feature. At Master level, graphic visualisation of the results is also expected.

    Several examples should be presented with networks of different scales, aiming to highlight the features of the simulation but also to analyse its performance and memory footprint.

    Requirements: good programming skills (Java or Python preferred), basics of networking

    Desired: basics of discrete event simulation, EMBS module

    Suitable for: BEng CS, BEng CSEmbSys, MEng CS, MEng CSEmbSys, MSc ACS

    Related work:
  • L. S. Indrusiak and O. M. dos Santos, Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration, 2011 Design, Automation & Test in Europe, 2011, pp. 1-6, doi: 10.1109/DATE.2011.5763179.
  • W. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004.
     

    lsi500.015 - Discrete-event simulation of routerless networks

    Routerless networks use ring topologies and packet deflection to achieve good communication performance without large overheads associated to buffering and routing. This project will involve the design and implementation of a fast and accurate simulator for routerless networks. While several simulators can be customised to simulate such networks, a simple and dedicated simulator for this particular kind of network can provide high performance and low memory footprint, which can be useful for the massively-parallel execution of simulations that are needed in optimisation processes.


    A successful project will produce a simulation environment that allows the instantiation of routerless networks with any arbitrary multi-ring topology, as well as packet producers and consumers attached to the network interfaces. Different choices for packet injection and ejection interfaces should be supported (shared, one-per-ring), and future extensibility should a desirable feature. At Master level, graphic visualisation of the results is also expected.

    Several examples should be presented with networks of different scales, aiming to highlight the features of the simulation but also to analyse its performance and memory footprint.

    Requirements: good programming skills (Java or Python preferred), basics of networking

    Desired: basics of discrete event simulation, EMBS module

    Suitable for: BEng CS, BEng CSEmbSys, MEng CS, MEng CSEmbSys, MSc ACS

    Related work:
  • F. Alazemi, A. AziziMazreah, B. Bose and L. Chen, Routerless Network-on-Chip, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018, pp. 492-503, doi: 10.1109/HPCA.2018.00049.
  • S. Liu et al., IMR: High-Performance Low-Cost Multi-Ring NoCs, in IEEE Transactions on Parallel and Distributed Systems, vol. 27, no. 6, pp. 1700-1712, 1 June 2016, doi: 10.1109/TPDS.2015.2465905.
     

    lsi500.016 - Data Analysis and Machine Learning for HF Radio Communications

    High Frequency (HF) Radio Communications are attractive due to the possibility of ionospheric refraction, which can enable global communication paths without using satellites or cables. The propagation of signals over such paths is notoriously difficult to predict, due to a many physical phenomena including atmosferic conditions and the solar cycle. This project will involve the analysis of a dataset produced by the supervisor, which includes hundreds of data points showing reception and successful transmission of digital data over HF at different frequencies, power levels, time of the day and of the year. The goal of the project is to analyse potential correlations between the different features of the data set, and attempt to create a model that can predict the success of a transmission attempt given enough information about the available communication channels.

    A successful project should analysise the dataset provided dataset, aiming to identify which features of the data can be most useful to predict the outcome of a transmission. Techniques to be considered include Principal Component Analysis or different types of machine learning. The evaluation of the project will be based on a separation of the dataset in training and evaluation data points, as well as using the system with live data and compare the prediction with the actual outcome of the data transmissions to be performed with the supervisor's experimental setup.

    Requirements: good analytical and programming skills

    Desired: AI, machine learning

    Suitable for: BEng CS, BEng CSEmbSys, MEng CS, MEng CSEmbSys, MSc ACS, MEng CSAI

    Related work::
  • A. Shenfield, Z. Khan and H. Ahmadi, Deep Learning Meets Cognitive Radio: Predicting Future Steps, 2020 IEEE 91st Vehicular Technology Conference (VTC2020-Spring), 2020, pp. 1-5, doi: 10.1109/VTC2020-Spring48590.2020.9129042.
     

    lsi500.017 - Simulation of Urban Airspace Resource Management

    Most commercial applications of Unmanned Aerial Systems (UASs) in urban environments - such as infrastructure surveillance, goods delivery and TV coverage of live events – require careful management of the airspace, in order to guarantee safe operation of the UASs themselves, other aircraft sharing the airspace and the population in general. UAS Traffic Management (UTM) systems, which focus on the management of low altitude airspace that can be used by UAS, are currently being discussed and regulated by national traffic management agencies worldwide. UTM systems are expected to operate with minimal human intervention, and will perform route planning, separation management, corridors, severe weather and wind avoidance, among other functions. One possible approach to UTM is the use of Airspace Service Providers (ASPs). ASPs are organised in a cellular network, each of them independently monitoring and managing their respective airspace sector, and handling protocols to hand over traffic to and from neighbouring sectors. Even though there are many uncertainties on the implementation of such approach, such as the interaction with existing traffic control authorities and weather data sources, the basic interactions between ASPs and UASs are fairly well understood and involve submission and authorisation of flight plans. This project focuses on this specific aspect of ASPs, and will investigate and implement a simulation tool to evaluate techniques and protocols that can guarantee separation and timeliness in all flight plans managed by an arbitrary group of ASPs.

    A successful project will implement simulation models of networks of ASPs, and will be able to evaluate different airspace management policies under different levels of demand (frequency and length of requested flight plans). At master level, it is expected that the simulation takes into account realistic data sources for terrain, buildings and weather to influence the result of the simulation.

    Requirements: good programming skills

    Desired: basics of discrete event simulation, EMBS module

    Suitable for: BEng CS, BEng CSEmbSys, MEng CS, MEng CSEmbSys, MSc ACS, MEng CSAI

    Related work::
  • National Aeronautics and Space Administration, Unmanned Aerial System (UAS) Traffic Management (UTM), Ames Research Center, 2014.
  • Google Inc, Google UAS Airspace System Overview, presented at the NASA Unmanned Aerial Systems Traffic Management Convention (UTM), 2015.

    lsi500.X - Student-defined project

    I will consider intelligent student-defined projects in the areas of concurrent and distributed embedded systems. I am interested in hardware, software or system-level approaches to the design and optimization of such systems. Send me an email with a few keywords and ideas and I'll send you some feedback.